Systemverilog Free Course: Udemy: VLSI Verification Courses: SV Beginner 1: Start with TB Construct

I am really thankful for all your efforts for us
Thank you so much
Your explanation is very clear and the pdf support is really good 😊

Really useful sir.thank you 🙏

Did u remove 10 hours video on sv?? pls reply

great video! can i have the slides?

hi, bro thanks for posting videos ,actually you giving a hope to enter in vlsi verification industry...but very much help full for me

I want to know whether you posted full content of system verilog or not . Do we need to join in the channel inorder to access system verilog content and UVM content ,can you clarify ??

Hi,

Great video helped me a lot,
U mentioned u will add downloadable resources, Iam not able to find that in description.
Can u check it once and share the material, it will be great help.

Thanks.

If we join for this channel with payment, what are the benefits we are going to get please 🤝

Hi,
really you shared worthless knowledge, how can I communicate to you for some thing to discuss regarding systemverilog and UVM verification, running and debugging,...it will be great help for us if you access to communicate to you, waiting for your reply 💐😊

Hi to join the academy is gpay option possible

Super brother good Explaination. Thanks brother

Hi,
Thanks for putting these videos here. The language used is easily understandable.
Please add more videos on UVM, it would be helpful for all of us. Thanks again

this is a very good course.. is it possible to share a few actual testbench examples where all these concepts so that we can get to learn more. Thanks

sir please make a video on memory protocol

Sir are you going to post all systemverilog videos?