Versal Embedded Design tutorial -- Adding the NoC (and DDR) to an existing Vivado project

This Versal Embedded Design Tutorial (EDT) series is an introduction for using the Xilinx® Vivado® Design Suite flow on a VMK180/VCK190 evaluation board. The tools used are Vivado® 2020.2 Design Suite and the Vitis™ 2020.2 unified software. These examples focus on introducing you to the useful aspects of embedded design. This tutorial introduces NoC (and DDR) configuration and related connections required for use with the CIPS. The Versal ACAP CIPS IP core allows you to configure two superscalar, multi-core Arm Cortex-A72 based APUs, two Arm Cortex-R5F RPUs, a platform management controller (PMC), and a CCIX PCIe® module (CPM). The NoC IP core allows configuring the NoC and enabling the DDR memory. This video uses the previous video tutorial design.

***Video timeline ***
0.30 Agenda
0.35 Step 1: Open the existing CIPS IP Project – Watch tutorial 1 video if you don’t have it ready. https://youtu.be/D-iUx3wxD5s
0.53 Adding the NoC IP to the block design
***Please source the below TCL command as suggested in the video
apply_bd_automation -rule xilinx.com:bd_rule:versal_cips -config { apply_board_preset {0} configure_noc {Add new AXI NoC} num_ddr {1} pcie0_lane_width {None} pcie0_mode {None} pcie0_port_type {Endpoint Device} pcie1_lane_width {None} pcie1_mode {None} pcie1_port_type {Endpoint Device} pl_clocks {None} pl_resets {None}} [get_bd_cells versal_cips_0]
*******
1:42 Step 2: Validating and Generating the design Output
2:38 Step 3: Generating the device image(PDI file)

Useful Resources:
Tutorial Link: https://github.com/Xilinx/Embedded-Design-Tutorials/tree/2020.2/Versal-EDT
Versal Example Designs
https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/487489537/Versal+Example+Designs

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