AMD 3D V-Cache for Ryzen CPUs is Impressive: Up to 192MB L3 Cache

Man they gave Ryzen very serious horse steroids

11 months later?
Where is the 5900x 3d??

why cant they but 1GB?

5775C vs 6700K in games...

they want you to buy v3 then buy zen4 after a couple of months :)

Big flexing by AMD here

So we are at the very end of the year. Isn't this supposed to be under production already? With at least a release date?

3D V-cache must be inspired from Samsung 3D V-NAND

Have 9900K, have good DDR4 rams, will upgrade to 3d-vcache ryzen9-5900x, I'll not buy Intel which forces me to buy 360mm aio...

Wow this is pretty impressive that Amd doesn’t even have to wait for it’s next architecture to compete with intels alder lake. Alder lake is rumored so far to be around 5 to 8 percent better in games when compared to current 5000 cpus. And if this cache does it’s 12 to 15 percent better gaming that’s pretty damn cool. Now it will be down to ddr5 maturity for next gen Ryzen I assume and will also benefit intel more later on as well.

A 3D V cache 5950x would OBLITERATE alder lake even with DDR5 & PCIe on its side…. Anywhere from 15-25% IPC uplift, generational performance increase on the transition from 3 to 3+ Zen that with ddr4 & pcie4 blows alder lake away still…. That’s funny

If that Intel processor ISNT 600$ like it was leaked to be priced at, there’s literally NO POINT in buying an Intel version of the Apple M1 chip…. Stupid

If M1 chips have shown that closer proximity ram gives significant performance gains why doesnt AMD just work with TSMC to integrate DRAM to the chips directly and then have a separate auxiliary channel for upgradable ram

I want to see the broadwell i7-5775c on that benchmark list 😂

Will it be on AM4?

You speak so fast and with this accent like you having something in your mouth, I understand English, but not your rythm), I always watch your videos with CC enabled, but this comes with Korean CC... WTF? I mean, CC is intended to show your language, you speaking English right? And no, its not auto translate, checked twice.

Ok, they're using HBM, nice, but...
Using a multistackdesign, they didn't take nto account that the stacks
can be much greater, even within a two mm slice for the whole stack
And it can also increase speeds for each stack added on top of the initial.
Since each memory unit pulses it's data, by multiplexing the data pathways,
the stack can in fact use up to 32 Gigabits per stack layer in a lane, across all stacks.
The question is timing of the multiplexing.
if you have like 10 layers, timing each datapulse for each stack layer is done by using
1/10th of each lane's time for each stack layer. This multiplexed signal is then 320 Gigabit.
(dependant/attenuated on the processor to receive such.)
Simultaneous requests across all stacks may yield a timing difference across
all of the stacks, when all stacks are being called for at the same time, and yet this
is a maybe 1-3 ns across all data across all stack layers.
The memory density as such can be increased many times,
well over HBM 3's current bandwidth.
Using 128 bits access and subsequently 128 lines, the maximum theoretical throughput
can be as high as 40960 Gigabits per second, across 128 lines.
(with 10 layers.)

Simply ask ALL to forward an answer if they have something applicable, and discard the ones
with zero in the 129th lane and only include the ones that have 1 in the 129th lane.
Since the memory responds in serial fashion for each bit, the received stream is then
in sequence, thanx to the atomic clock.
Afore mentioned 1-3 ns, is per IOPS, not per bit, so asking for 64K of data, has less
latency per bit forwarded than each byte seperately, since this would be one IOPS per byte.

it means cs go and valorant will be fps monster :):)

jesus the precision for mounting that little wafer on top is incredible! :O

I seem to recall a while back it being discussed that the thickness of a zen3 die was a little smaller and there was concern it might affect existing am4 cooling solutions. I guess this might be a possible reason for shedding some height off the core package. Split the height difference so that everything still works on the same gear?

2nd viewing: You're basically saying AMD has found a way to apply hbm2 stacking to cache, which is amazing. If I remember correctly you get added bandwidth as you stack hbm2's. That's remarkable for upcoming CPU & GPU.

I hope this 3d cache Ryzen will remain on am4 (just bought an x570 mobo) and would also cover the ryzen 5 family

my question is how does 3D stacking handle heat dissipation--won't there be more thermal density?

Just shows with all the IPC increases cores are being starved. Anymore IPC increases won’t be as good as is the limiting factor.

NICE AWES0ME C00L_ 🍨 VIEW *

3D v cache cpus mean same b550 mobo?

This is really thick, last time I was this deep in technology, I was still trying to download moar ram.

Amazing tech from AMD, they just don't stop do they?

I keep creating clusters from old home computers and the older ones I have are getting obsolete so fast now. Compute density is just getting insane to the point it’s a waste of electricity to keep some of the older ones around

will AMD ever stop their killing spree or are they gonna keep releasing faster CPU's and new technology every other year?
like, what's up with that?
did they find some spaceship or something and they pretend to develop better technology but really they just wanna slowly release the stuff they found so they're not sus?

also, I think it would be interesting to compare the new AMD CPU's to the first gen like the 1800x.
Intel propably is not gonna stay relevant for long now, except for low budget builds....quite ironic...

this could be revolutionary if it doesn't tank thermals - especially when competitively pushing the design as it evolves

Anyone get a feeling that they'll use the same zen3 architecture but add the 3d chiplet on top?

I wonder how this affects temps?

Many credits goes to TSMC

When FSR is on, the resolution seems much worse (lower). Frame rate is higher, but quality is a LOT worse. I've seen this in several other reviews, but no-one seems to be commenting on it! C'mon Steve, WTF is going on here? 'Quality Mode'!!! LOWER Quality Mode maybe?!? This is NOT impressive. A joke would be a more appropriate comment IMO. The guys at HarwareUnboxed noticed it, but glossed over it!

The 3D cache is going to be interesting when mining monero. As well as core count cache plays a huge part in CPU mining...can't wait.

Hey, Subtitles are in Corean ? Please enable automatic English subtitles. It helps a lot ! Thanks.

Imagine mining Monero with that thing!

👍

I wonder what thermals will really be like?
Can’t wait to find out
🙃

lol thinking ryzen or any x64 cpus still matter when apple M1 is a thing. Anything but an M1 mac are e waste, including 2019 intel macs.

This dude needs to make "Gamers Nexus Hair Clips"

your hesitancy on FSR is unfounded. AMD is committed to this because they need to compete with DLSS. it will happen and it will be the future.

Someday AMD will create an asymmetrical architecture with 8 GB of onboard high performance ram and then an external RAM slot to increase it from there

We should run Windows 7 without ram. Purely in cache

Wow, really impressive from AMD. They really aren't resting on their laurels, which is great to see. I didn't expect this so quickly.
I'm a big fan of more cache, so this is great to see. It could get pretty crazy for Zen4 if they optimize the whole layout to be able to connect to as much V-cache as possible.
It's difficult for me to understand how you can stack a layer on top of the cores and not have that result in a thermal penalty though. Even if they managed to thin the cores down to keep the same package size, assuming the cores are physically further from the cooler and also have some heat generated above them... but I guess we'll see.

Lets Hope this Will not end up like the radioen 56 cards where HBM was really bad at overclocking hindring the proformance of the entire gpu card. If this L3 has the same gearing problem this Will only help server side systems leaving gamers with overpriced underproformers

Now I want to see an APU with the extra SRAM CACHE... I imagine the 1% & 0.1% lows would be much closer to their averages. Maybe even faster overall.

when you think those gains are brute force and that games are not optimized to take advantage of such a technology. Once they are, the difference will be even bigger. This tech will probably be on next-gen consoles in 2026-2027.